Learning Objectives
- Describe the functions of the address, data and control buses.
- Explain the direction of travel and typical contents of each bus.
- Describe the fetch, decode and execute stages in the correct sequence.
- Explain how the named registers are used during an instruction fetch.
- Trace a simple instruction through the processor using register transfers and control signals.
Key Terms
- Bus
- A set of parallel electrical pathways used to carry information between components.
- Address bus
- The bus that carries the address of the memory or input/output location being accessed.
- Data bus
- The bus that carries data and instructions between the processor, memory and other devices.
- Control bus
- The bus that carries control signals, such as read, write and timing signals.
- Fetch
- The stage in which the next instruction is obtained from memory.
- Decode
- The stage in which the control unit interprets the instruction.
- Execute
- The stage in which the required operation is carried out.
- Read signal
- A control signal requesting that a value be supplied from memory or a device.
- Write signal
- A control signal requesting that a value be stored in memory or sent to a device.
- Opcode
- The part of an instruction that identifies the operation to be performed.
- Operand
- The part of an instruction that identifies a value, register or address used by the operation.
The Address Bus
The address bus carries the address of the location that the processor wants to access. During a memory read or write, the address held in the memory address register is placed on the address bus. Memory uses that binary address to select one location.
The address bus normally carries information from the processor to memory or an input/output interface, so it is described as unidirectional. The number of lines in the address bus determines how many different addresses can be represented. For example, an address bus with n lines can represent 2 to the power n distinct address patterns.
In examination answers, do not say that the address bus carries the data stored at the address. It carries the identity of the location. The data itself travels on the data bus.
The Data And Control Buses
The data bus carries the actual binary information being transferred. This may be an instruction fetched from memory, a data value read from memory, or a result being written back. Because information can travel to or from the processor, the data bus is bidirectional.
The control bus carries the signals that coordinate a transfer. A read signal tells memory to place the contents of a selected address onto the data bus. A write signal tells memory to store the value currently on the data bus. Other control signals can coordinate timing, interrupts and device operations, but answers should focus on the required purpose: controlling and coordinating components.
All three buses work together. The address bus identifies where, the data bus carries what, and the control bus indicates what action is required.
The Fetch Stage
At the start of the fetch stage, the program counter contains the address of the next instruction. This address is copied into the memory address register. The address is then sent to memory on the address bus while the control unit sends a read signal on the control bus.
Memory returns the instruction on the data bus. The instruction is placed in the memory data register and then copied into the current instruction register. The program counter is incremented so that it points to the next instruction in sequence. The order of incrementing can be described slightly differently in diagrams, but the final result is that the PC normally identifies the following instruction.
A complete fetch explanation should name the PC, MAR, MDR and CIR and should identify the use of the address, data and control buses.
Decode And Execute
During decode, the control unit interprets the instruction in the current instruction register. It identifies the opcode and determines what operands or additional data are required. The control unit then generates the control signals needed for execution.
The execute stage depends on the instruction. The ALU may perform arithmetic or a comparison. Data may be copied between registers. A value may be read from or written to memory. An input or output device may be used. A branch instruction may replace the value in the program counter so that the next fetch comes from a different address.
After execution, the cycle begins again. A processor repeats this cycle continuously while a program is running. The phrase fetch-decode-execute describes a cycle, not a process that happens only once.
The Three System Buses
| Bus | Carries | Usual Direction | Example |
|---|---|---|---|
| Address bus | A memory or device address. | From CPU to memory or device. | The address held in the MAR. |
| Data bus | Instructions and data values. | Both to and from the CPU. | A fetched instruction or a calculated result. |
| Control bus | Signals coordinating operations. | Both directions depending on the signal. | Read, write or interrupt signal. |
Fetch-Decode-Execute Sequence
| Stage | Key Actions | Main Components |
|---|---|---|
| Fetch | Copy next address, request memory read, receive instruction and update PC. | PC, MAR, MDR, CIR, buses and memory. |
| Decode | Interpret opcode and identify required operands or action. | CIR and control unit. |
| Execute | Carry out arithmetic, logic, transfer, input/output or branch operation. | ALU, registers, memory and devices as required. |
Worked Examples
Tracing An Instruction Fetch
Question: The PC contains 240. Describe the register transfers used to fetch the instruction at that address.
- Copy 240 from the PC to the MAR.
- Place 240 on the address bus and send a read signal on the control bus.
- Memory sends the instruction on the data bus to the MDR.
- Copy the instruction from the MDR to the CIR.
- Increment the PC so that it normally contains the next instruction address.
Answer: PC to MAR; memory read; instruction to MDR; MDR to CIR; PC updated.
Choosing The Correct Bus
Question: A calculated result must be stored at memory address 700. Identify how each bus is used.
- The address 700 is placed on the address bus.
- The calculated result is placed on the data bus.
- A write signal is sent on the control bus.
- Memory stores the result at address 700.
Answer: Address bus carries 700, data bus carries the result and control bus carries the write signal.
Examination Guidance
- Use the concise pattern: address bus says where, data bus carries what, control bus says what action.
- State that the address bus is normally unidirectional and the data bus is bidirectional.
- In a fetch answer, include the register transfers PC to MAR and MDR to CIR.
- Do not stop after fetch; decode means interpret, while execute means carry out the operation.
- Mention that a branch can change the PC rather than simply incrementing it.
Common Mistakes
- Saying the address bus carries the contents of memory.
- Saying the data bus is unidirectional.
- Omitting the memory-read control signal during fetch.
- Placing the fetched instruction directly in the MAR.
- Describing decode as the stage where the ALU always performs a calculation.
Knowledge Check
1. What does the address bus carry?
2. Why is the data bus bidirectional?
3. Which register supplies the address during a normal fetch?
4. Where is the fetched instruction held for decoding?
5. What happens after an instruction is executed?
